1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly, to a method of fabricating an oxide-nitride-oxide ONO electrically erasable and programmable read only memory EEPROM device having two transistors for performing two bit operations, and a method of driving the ONO EEPROM device.
2. Description of Related Art
An ONO EEPROM device is one type of non-volatile semiconductor memory device and has an oxide-nitride-oxide (ONO) layer in the bottom of a gate. The nitride layer in the ONO EEPROM device is a dielectric layer trapping or de-trapping electrons for data programming, data erasing, and data readout in a memory cell.
Generally, the ONO EEPROM device applies a Fowler-Nordheim (F-N) tunneling phenomenon or channel hot electron injection (CHEI) to trap electrons. The F-N tunneling method consumes less current to trap electrons, but has longer trapping time. In contrast, the CHEI method has shorter trapping time, but consumes more current to trap electrons so that the number of electron-trapping cells is limited.
U.S. Pat. No. 5,768,192 discloses an ONO non-volatile memory device applying the CHEI method to trap electrons in the nitride layer. FIG. 1a illustrates a cross sectional configuration for a unit cell of a conventional ONO EEPROM device applying a CHEI method to write a data, that is, to program a data. FIG. 1b shows an equivalent circuit diagram for the unit cell of the conventional ONO EEPROM device.
Referring to FIG. 1a and FIG. 1b, the unit cell of the conventional ONO EEPROM device 10 comprises a cell transistor CT11 having a conductive gate 30 connected to a word line WL11 and source/drain junction areas 41 and 42 connected to a pair of bit lines BL11 and BL12, respectively.
The conventional ONO EEPROM device comprises a trapping dielectric layer 25 with the ONO structure stacking serially a bottom oxide layer 21, a nitride layer 22, and a top oxide layer 23 on a silicon substrate of a first conductive type, for example, on a channel area 43 of a p-type silicon substrate 20.
The conductive gate 30 connected to the word line WL11 is formed on the trapping dielectric layer 25. The source/drain junction areas 41 and 42 are formed on the silicon substrate 20, below both sides of the conductive gate 30, and are overlapped with the conductive gate 30.
The bottom oxide layer 21 of the trapping dielectric layer 25 is an electric isolation layer for the channel area 43 and the top oxide layer 23 is an electric isolation layer for the word line WL11. The nitride layer 22 between the bottom oxide layer 21 and the top oxide layer 23 is an electron-trapping layer for data retention.
The above described conventional EEPROM device applies pre-determined voltages to the conductive gate 30 and to a pair of bit lines, BL11 and BL12, connected to the source/drain junction areas 41 and 42, respectively. Therefore, the electrons in the channel layer are trapped on the nitride layer 22 so that data is written in a corresponding memory cell.
The conventional EEPROM device applies the CHEI method to program data to a memory cell. The CHEI method requires a considerable amount of current for writing data to numerous memory cells. Therefore, a confined amount of current also limits the number of memory cells for writing data.
In addition, excessive electron de-trapping in an electron-trapping layer generates disturbance phenomena for erasing data in a memory cell when the data in the memory cell of the conventional EEPROM device is erased, which results in lowering device reliability of the conventional EEPROM device.
To overcome the above-described problems in conventional technology, the present invention provides a fabricating method of an ONO EEPROM device improving electron trapping efficiency and reducing trapping current, and a method of driving the ONO EEPROM device thereof.
Another purpose of the present invention is to provide a fabricating method of an ONO EEPROM device employing a split word line to improve electron-trapping efficiency in the CHEI method, and a method of driving the ONO EEPROM device thereof.
Another purpose of the present invention is to provide a fabricating and driving method of an EEPROM device employing a split word line with an ONO dielectric layer to form two memory cells between a pair of bit lines, and thereby improve integration degree of the EEPROM device.
Another purpose of the present invention is to provide a fabricating and driving method of an EEPROM device preventing disturbance phenomena from erasing data to improve reliability of the EEPROM device.
Another purpose of the present invention is to provide a fabricating and driving method of an ONO EEPROM device having two transistor cells between a pair of bit lines, and employing each of the transistor cells as a selection transistor cell to improve disturbance immunity of the EEPROM device.
Another purpose of the present invention is to provide a fabricating and driving method of an ONO EEPROM device applying a self-align method to generate a split word line, thereby reducing cell size.
The present invention is directed to a non-volatile memory device which includes a silicon substrate of a first conductivity type having first and second channel areas adjacent each other. First and second conductive gates are formed on the first and the second channel areas facing each other. First and second insulation layers are formed on the bottoms of the first and the second conductive gate, and on the silicon substrate between the first and the second conductive gate. First and second junction areas of a second conductivity type are formed in the silicon substrate overlapping with the first and the second conductive gate, wherein the first and the second channel areas are defined as a space between the first and the second junction areas.
In one embodiment, the first conductive gate is a control gate and the second conductive gate is a selection gate. Alternatively, the first conductive gate is a selection gate and the second conductive gate is a control gate.
The first and the second insulation layers can include ONO layers including a nitride layer between oxide layers as an electron trapping layer.
The portion of the ONO layers formed in the bottom of the first and the second conductive gates functions as dielectric layers for trapping electrons, and the portion of the ONO layers formed between the first and the second conductive gates functions as an insulation layer.
The present invention is also directed to a non-volatile memory device comprising: a silicon substrate of a first conductivity type including first and second channel areas adjacent each other; first and second conductive gates formed on the first and the second channel areas, respectively, facing each other; first and second, including electron trapping layers, formed in the bottom of the first and the second conductive gates, and on the silicon substrate between the first and the second conductive gates; and first and second junction areas of a second conductivity type formed in the silicon substrate overlapping with the first and the second conductive gates, wherein the first and the second channel areas are defined as a space between the first and the second junction areas, the non-volatile memory device uses one of the conductive gates as a selection gate while the other of the conductive gates functions as a control gate so that the conductive gates are driven independently from each other, and applies an electric field to the control gate to trap electrons of a channel area in the bottom of the selection gate to the electron trapping layer of the dielectric layers in the bottom of the control gate so that each bit data is respectively stored in each of the dielectric layers.
The present invention is also directed to a non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell having first and second memory cells connected between the pair of bit lines, wherein the first memory cell formed in a first channel area of a first conductivity type silicon substrate comprises: a first conductive gate connected to one word line of the pair of word lines; a first dielectric layer including an electron trapping layer formed in the bottom and a side wall of the first conductive gate; and a first junction area of a second conductivity type which is connected to one bit line of the pair of bit lines being overlapped with the first conductive gate, and wherein the second memory cell formed in a second channel area facing the first conductive gate, comprises: a second conductive gate connected to the other word line of the pair of word lines; a second dielectric layer including an electron trapping layer formed in the bottom and a side wall of the second conductive gate; and a second junction area of the second conductivity type which is connected to the other bit line of the pair of bit lines, and overlapped with the second conductive gate.
The first and the second dielectric layers can include corresponding first and second ONO layers, each including a nitride layer between oxide layers as an electric trapping layer.
The present invention is also directed to a non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell having first and second memory cells connected between the pair of bit lines, wherein the first memory cell formed in a first channel area of a first conductivity type silicon substrate, comprises: a first conductive gate connected to one word line of the pair of word lines; a first dielectric layer including an electron trapping layer formed in the bottom and a side wall of the first conductive gate; and a first junction area of a second conductive type which is connected to one bit line of the pair of bit lines being overlapped with the first conductive gate, and wherein the second memory cell formed in a second channel area facing the first conductive gate, comprises: a second conductive gate connected to the other word line of the pair of word lines; a second dielectric layer including an electron trapping layer formed in the bottom and a side wall of the second conductive gate; and a second junction area of the second conductivity type which is connected to the other bit line of the pair of bit lines, and overlapped with the second conductive gate, the non-volatile memory device uses one of the memory cells as a data cell for storing data, and the other of the memory cells functions as a selection cell for selecting a cell so that each of the memory cells store one bit data.
In one embodiment, the non-volatile memory device programs data to a data cell, wherein: a first high voltage is applied to one bit line of the pair of bit lines connected to the junction area of the data cell; the other bit line of the pair of bit lines connected to the junction area of the selection cell is grounded; the substrate of the first conductivity type is grounded; a second high voltage is applied to one word line of the pair of word lines connected to the conductive gate of the selection cell; and a low voltage is applied to the other word line of the pair of word lines connected to the conductive gate of the data cell.
In one embodiment, the non-volatile memory device erases the programmed data of the data cell, wherein: the first high voltage is applied to one bit line of the pair of bit lines connected to the junction area of the data cell; the low voltage is applied to the other bit line of the pair of bit lines connected to the junction area of the selection cell, and to one word line of the pair of word lines connected to the conductive gate of the selection cell; the other word line of the pair of word lines connected to the conductive gate of the data cell is grounded; and the substrate is grounded.
In one embodiment, the non-volatile memory device reads the programmed data from the data cell, wherein: one bit line of the pair of bit lines connected to the junction area of the data cell is grounded; the substrate of the first conductivity type is grounded; a readout voltage is applied to the other bit line of the pair of bit lines connected to the junction area of the selection cell; a readout voltage is also applied to one word line of the pair of word lines connected to the conductive gate of the data cell; and the low voltage is applied to the other word line of the pair of word lines connected to the conductive gate of the selection cell.
In one embodiment, the first high voltage is 8 to 10 V; the second high voltage is 9 to 12 V; the low voltage is 4 to 5 V; and the readout voltage is a value between a programming threshold voltage and an erasing threshold voltage to the data cell.
The junction area of the selection cell can functions as a source area of the data cell in programming a data.
The present invention is also directed to a non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell connected between the pair of bit lines, wherein each of the conductive gates is connected to each word line of the pair of word lines, the non-volatile memory device stores one-bit data to each of the transistors.
The present invention is also directed to a non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell, connected between a pair of bit lines, comprising a pair of transistors with two terminals. The non-volatile memory device connects one terminal of the pair of transistors to the pair of word lines, respectively, and the other terminal of the pair of transistors to the pair of bit lines, respectively.
In one embodiment, one transistor of the pair of transistors functions as a cell transistor, and the other of the pair of transistors functions as a selection transistor so that each of the pair of transistors stores one-bit data independently from each other.
In one embodiment, the non-volatile memory device programs data to a selected transistor of the pair of the transistors in the unit cell, wherein a first high voltage is applied to one bit line of the pair of bit lines connected to the selected transistor; a second high voltage is applied to one word line of the pair of word lines connected to the selected transistor; a low voltage is applied to the other bit line of the pair of bit lines connected to the non-selected transistor; a ground voltage is applied to the other word line of the pair of word lines connected to the non-selected transistor.
In one embodiment, the non-volatile memory device erases the programmed data of the selected transistor, wherein the first high voltage is applied to one bit line of the pair of bit lines connected to the selected transistor; the low voltage is applied to one word line of the pair of word lines connected to the selected transistor; the low voltage is applied to the other bit line of the pair of bit lines connected to the non-selected transistor; and the ground voltage is applied to the other word line of the pair of word lines connected to the non-selected transistor.
In one embodiment, the non-volatile memory reads the programmed data from the selected transistor, wherein the ground voltage is applied to one bit line of the pair of bit lines connected to the selected transistor; a readout voltage is applied to one word line of the pair of word lines connected to the selected transistor; a readout voltage is also applied to the other bit line of the pair of bit lines connected to the non-selected transistor; and the ground voltage is also applied to the other word line of the pair of word lines connected to the non-selected transistor.
In one embodiment, the selected transistor functions as a cell transistor and the non-selected transistor functions as a selected transistor.
In one embodiment, the first high voltage is 8 to 10 V; the second high voltage is 9 to 12 V; the low voltage is 4 to 5 V; and the readout voltage has a value between a threshold voltage of programming a data and a threshold voltage of erasing a data.
The present invention is also directed to a method of programming bit data to a first and a second memory cell of a unit cell in a non-volatile memory device independently from each other, comprising a pair of bit lines, a pair of word lines, and a unit cell between the pair of bit lines including a first and a second memory cell, wherein the first and the second memory cell are respectively formed in the first and the second junction area on the silicon substrate, wherein the first and the second memory cell comprise conductive gates including an electron trap layer generated in the above channel area, and junction areas of the second conductive type, overlapped with the conductive gate, formed on the substrate, and connected to each bit line of the pair of bit lines, and wherein one of the first and the second memory cell functions as a data cell for storing a data and the other of the first and the second memory cell functions as a selection cell for selecting a cell, and each of the first and the second memory cell store one-bit data, the method of programming data comprising the step of: applying a ground voltage to one bit line of the pair of bit lines of the selection cell, and a low voltage to one word line of the pair of word lines of the selection cell; applying high voltages to the other bit line of the pair of bit lines of the data cell, and to the other word line of the pair of word lines of the data cell; and trapping electrons in the channel area of the selection cell to electron trapping layer of the data cell by the high voltage applied to the other word line of the pair of word lines of the data cell.
The present invention is also directed to a method of erasing bit data of a first and a second memory cell of a unit cell in a non-volatile memory device independently from each other, comprising a pair of bit lines, a pair of word lines, and a unit cell between the pair of bit lines including a first and a second memory cell, wherein the first and the second memory cell are respectively formed in the first and the second junction area on the silicon substrate, wherein the first and the second memory cell comprise conductive gates including an electron trap layer generated in the above channel area, and junction areas of the second conductive type, overlapped with the conductive gate, formed on the substrate, and connected to each bit line of the pair of bit lines, and wherein one of the first and the second memory cell functions as a data cell for storing data and the other of the first and the second memory cell functions as a selection cell for selecting a cell, and each of the first and the second memory cell store one-bit data, the method of erasing data comprising the step of: applying a low voltage to one bit line, and to one word line of the pair of word lines of the selection cell; applying a high voltage to the other bit line of the pair of bit lines of the selection cell, and a ground voltage to the other word line of the pair of word lines of the selection cell; and injecting holes formed in the channel area of the selection cell to electron injection layer by the ground voltage applied to the other word line of the pair of word lines of the selection cell.
To achieve a purpose according to the present invention, the present invention discloses a method of reading a bit data from a first and a second memory cell of a unit cell in a non-volatile memory device independently from each other, comprising a pair of bit lines, a pair of word lines, and a unit cell between the pair of bit lines including a first and a second memory cell, wherein the first and the second memory cell are respectively formed in the first and the second junction area on the silicon substrate, wherein the first and the second memory cell respectively comprise conductive gates including an electron trap layer generated in the above channel area, and junction areas of the second conductive type, overlapped with the conductive gate, formed on the substrate, and connected to each bit line of the pair of bit lines, and wherein one of the first and the second memory cell functions as a data cell for storing a data and the other of the first and the second memory cell functions as a selection cell for selecting a cell, and each of the first and the second memory cell store respectively one bit data, the method of reading a data, comprising the step of: applying a readout voltage to one bit line of the pair of the bit lines of the selection cell and a low voltage to one word line of the pair of word lines of the selection cell; applying a ground voltage to the other bit line of the pair of bit lines of the selection cell, and a readout voltage to the other word line of the pair of word lines of the selection cell; and reading a stored data in the selection cell according to on/off of the data cell.
The present invention is also directed to a fabrication method of a non-volatile memory device comprising the steps of: supplying a silicon substrate of a first conductive type; fabricating an insulation layer having a window for exposing a predetermined area of the silicon substrate; fabricating a first conductive gate in a spacer shape, comprising a fist dielectric layer in a side wall of the insulation layer within the window; etching back the insulation layer; fabricating a second conductive gate in a spacer shape in a side wall of the first conductive gate, comprising a second dielectric layer and facing the first conductive gate; fabricating junction areas of a second conductive gate overlapping with the first and the second conductive gate.
In one embodiment, the insulation layer comprises a pad oxide layer and a nitride layer formed on the silicon substrate.
In one embodiment, each of the first and second dielectric layers comprises an oxide a nitride an oxide ONO layer.
In one embodiment, the first and the second dielectric layers fabricated between the first and the second conductive gate facing each other insulate the first and the second conductive gate from each other.
In one embodiment, each of the first and second conductive gates comprises a polysilicon layer.
In one embodiment, the fabrication method of the first conductive gate including the first dielectric layer comprises: fabricating a first ONO layer including a first oxide layer, a nitride layer and a second oxide layer upon the insulation layer including the window; fabricating a polysilicon layer on the second oxide layer of the first ONO layer; and fabricating the first dielectric layer and the first conductive gate in a side wall of the window by an etch-back process for the first ONO layer and the polysilicon layer.
In one embodiment, the fabrication method of the second conductive gate including the second dielectric layer comprises: fabricating a second ONO layer including a first oxide layer, a nitride layer and a second oxide layer on the silicon substrate including the first conductive gate; fabricating a polysilicon layer on the second oxide layer of the second ONO layer; and fabricating the second dielectric layer and the second conductive gate in a side wall of the first conductive gate by an etch-back process for the second ONO layer and the polysilicon layer.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.